D&R Industry Articles (December 2018)

Featured Article

Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms

We start this article by defining “RAS” in the context of PCIe interfacing and looking at the provisions for RAS mechanisms in the PCIe Specification. We then explore some potential PCIe hazards SoC designers can face and the RAS mechanisms that can be implemented to detect, recover, or prevent these hazards. We conclude with recommendations for choosing a PCIe silicon IP solution that helps mitigate these risks.

Featured Article

Extending 8K over a single, cost-effective wire with TICO lightweight compression

With HD omnipresent and 4K seemingly still in its early stages, an even higher resolution, namely 8K (or UHDTV2) is arising. Display and projection manufacturers are already presenting their first 8K-capable products and the 2018 Winter Olympics were partly filmed in this currently largest video resolution format. Taking a peek into the future, Japan’s national TV “NHK” has even announced to broadcast the full Olympic games on home turf in 2020 in glorious 8K.

Featured Article

PCI Express 3.0 needs reliable timing design

PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard.