D&R Industry Articles (September 2019)

Featured Article

Implementing Secure Boot in Your Next Design

The number of new viruses and malwares created every day is getting close to 1 million. Thus, in an always more connected world, getting protected against these attacks becomes absolutely critical. To make a device trustable one needs to make sure it runs only genuine firmware.

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How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity

An FPGA-based SmartNIC employs the expanded hardware programmability of FPGAs to build any data-plane functions required by the tasks offloaded to the SmartNIC. Because FPGAs are reprogrammable, the data-plane functions implemented by the FPGA can be torn down and reconfigured at will and in real time. All such offloaded functions operate at hardware – not software – speeds.

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The Age of the Monster Chip

What are the system designs that require a leap in SoC complexity? It's not only big datacenter artificial intelligence (AI) chips, but also autonomous vehicles such as cars, trucks and drones; they are self-landing, reusable rockets; they are medical devices carrying out remote diagnostics.

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Better Benchmarks through Compiler Optimizations: Codasip Jump Threading

The architectural efficiency of embedded processor IP is measured by a small set of industry standard benchmarks, that even though often bear little correlation to real workloads, continue to persist. The most popular benchmarks are Dhrystone and CoreMark.

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UVM RAL Model: Usage and Application

To cope with the speed of the competitive market landscape, most of the systems are designed in a generic way - which means the same design can be used in different ways with different configurations. More the number of configurations, more the number of registers in the design.