D&R Industry Articles (January 2020)

Featured Article

Interface Timing Challenges and Solutions at Block Level

In this article, we will address the challenges faced while fixing the interface timing and the solutions to overcome these challenges. We have used Cadence Innovus as our PnR and Synopsys Primetime as our Sign-off timing tool.

Featured Article

Setup Margin Aware Quick Hold Fixing

Static Timing Analysis (STA) is a key factor to validate while manufacturing a chip, where each design must go for setup and hold validation. In today’s era, technology nodes are shrinking and crosstalk plays a major role in timing along with cell-net delay. In addition, accounting derate (OCV/AOCV/POCV) is to overcome PVT uncertainties of the chip.

Featured Article

Securing Smart Connected Homes with OTP NVM

The market for piracy is huge and hackers have become increasingly sophisticated even when security is implemented in hardware. The race between the aggressors and protectors is a battle without end. Smart connected home devices are increasingly storing and processing very sensitive and private user data in addition to attempting to deliver copyright protected content from service providers. Protecting consumer data is vital.