D&R Industry Articles (June 2020)

Featured Article

Analog and Power Management Trends in ASIC and SoC Designs

The design of modern Application Specific Integrated Circuits (ASICs) and Systems on a Chip (SoCs) in advanced process nodes can be differentiated by the on-die integration of analog functions, such as power management. Vidatronic offers this white paper to give some historical background on this trend and delve specifically into the integration of power management. Vidatronic IP solutions and the benefits they bring to ASIC and SoC designers are discussed.

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Where Innovation Is Happening in Geolocation. Part 1: Signal Processing

At first glance, geolocation technology seems to work well. Our phones and cars get us to where we need to be with little effort and rather reliably. For consumers, it’s a free service, thanks to service providers like Google and Apple.

Featured Article

GRSCRUB: FPGA Configuration Supervisor

The GRSCRUB is an external Field Programmable Gate Array (FPGA) configuration supervisor developed by Cobham Gaisler as an Intellectual Property (IP) core. The GRSCRUB IP features different capabilities, such as programming and scrubbing, which prevents the accumulation of errors in the configuration memory of SRAM-based FPGAs.

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Breaking new energy efficiency records with advanced power management platform

The free lunch offered for decades by Moore’s law is now over and scaling down to the next technology node no longer offers the required energy efficiency gains. Design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the demands of the new IoT markets.

Featured Article

Time-Domain Analog Design: Why and How

The widespread adoption of scaled CMOS process technologies has made battery-operated consumer devices more powerful, cheaper, and last longer. In the last two decades, CMOS technology scaling has resulted in orders of magnitude reduction in transistor sizes, from 90nm in 2004 to 7nm in 2019 and 3nm in 2024.