D&R Industry Articles (November 2020)
Articles for the Week of November 30, 2020
Gathering Regression List for Structural Coverage Analysis
Structural coverage analysis is a method to ensure RBTs parse the code structure to verify every line of code for its correctness. RBTCA is used to determine the efficiency our tests verifying implementation of the software requirements. The intention is to check whether code and requirements are in sync.Articles for the Week of November 23, 2020
The Future Of Chip Design
The future of chip design in a few short years could look entirely different as the semiconductor industry witnesses an advancing trend toward free and flexible, community-supported hardware designs for the long tail of new applications based on custom semiconductor devicesArticles for the Week of November 16, 2020
Seize the Ethernet TSN Opportunity
The following sections will take a look at the major Ethernet performance issues and how the extensions address those shortcomings. This will be followed by an overview of the applications of TSN for 5G, industrial automation, automotive invehicle communications and avionics. The paper will conclude with a description of Ethernet TSN solutions offered by Comcores.Articles for the Week of November 9, 2020
A MAC-less Neural Inference Processor Supporting Compressed, Variable Precision Weights
This paper introduces two architectures for the inference of convolutional neural networks (CNNs). Both architectures exploit weight sparsity and compression to reduce computational complexity and bandwidth.- Solving the problem of growing ASIC respins
- Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow
Articles for the Week of November 2, 2020
Solving a problem like reuse
To invest the time and resources in reusing an analog IP requires a judgement call on the potential returns from the market and the time it takes to get the IP to that market to generate revenue is key – if a competitor project hits the market first, then the potential returns are greatly diminished.- Avoid HPC Data Traffic Jams with High-Speed Interface IP
- ISA optimizations for hardware and software harmony: Custom instructions and RISC-V extensions