D&R Industry Articles (September 2023)

Featured Article

Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)

The objective of this paper is to illustrate congestion, shorts, and practical approaches to fix both issues at lower/higher technology nodes. This paper also includes PnR tool (ICC2) related commands and their uses to overcome the mentioned issues.

Featured Article

Accelerating RISC-V development with network-on-chip IP

In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.

Featured Article

I2C Interface Timing Specifications and Constraints

This paper covers the timing specification of I2C (Inter-Integrated Circuit) bus protocol. We have described all the timing specifications and how they are achieved by constraining our design. This paper focuses on the timing constraints for fast mode plus (The data transfer rate is 1 Mbit/s).

Featured Article

Handling the Challenges of Building HPC Systems We Need

What is the secret of humanity’s success? What has given us the ability to build wonders, such as Stonehenge in England, the Pyramids of Egypt and the Great Wall of China? Humans are small, weak and slow compared with many other animals.