D&R Industry Articles (May 2024)

Featured Article

Using PSS and UVM Register Models to Verify SoC Integration

One particularly challenging stage of SoC development is verifying that the complete design has been assembled correctly. This requires checking to be sure that both the software and hardware do what they are intended to do. Automating much of this process is possible using a combination of the Portable Stimulus Standard (PSS) and Universal Verification Methodology (UVM) register models.

Featured Article

Why verification matters in network-on-chip (NoC) design

In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.

Featured Article

An Introduction to Post-Quantum Cryptography Algorithms

The rise of quantum computing paints a significant challenge for the cryptography we rely on today.

Featured Article

Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)

The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads.