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20 Most Popular Articles

Updated: Fri, 02 May 2025 01:00:02 +0200

Today		Yesterday
	1	1	System Verilog Assertions Simplified Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains the concurrent assertions syntaxes, simple examples of their usage and details of passing and failing scenarios along with waveform snippets for the ease of understanding.
	2	2	System Verilog Macro: A Powerful Feature for Design Verification Projects SV macro is one of the most powerful features out there and if used properly with a thorough understanding and applied wisely in a DV project, it can help to save a lot of time and can make the code more readable and efficient. This paper shows how, using SV macro with the proper syntaxes, a DV engineer can break up the larger complex code in smaller chunk and can reuse it at many places.
	3	8	Scan Chains: PnR Outlook At times physical design engineers find it difficult to relate with the additional timing modes introduced in PnR due to DFT insertion. These additional timing modes and related issues could be handled more efficiently if we understand why a scan chain is needed and how it works.
	4	9	UPF Constraint coding for SoC - A Case Study This paper deals with the implementation of UPF for low power SoC design that can encompass several vendor IPs and custom IPs UPF constraints.
	5	12	Design Rule Checks (DRC) - A Practical View for 28nm Technology The main objective of this paper is to explain the various types of design rule checks (DRC) violation, their causes and how to fix the various design rule checks (DRC) at lower technology node on block level as well as full chip level implementation while meeting the design rule with respect to latest technology standards.
	6	4	Method for Booting ARM Based Multi-Core SoCs In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.
	7	11	PCIe error logging and handling on a typical SoC This paper details first PCIe errors, error logging and then the error handling on a typical SoC.
	8	New!!!	Dynamic Memory Allocation and Fragmentation in C and C++ In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issues is not an option.
	9	3	Optimizing Analog Layouts: Techniques for Effective Layout Matching In analog layout design, precise layout matching techniques are crucial to ensure the accuracy and performance of the circuit so that transistors exhibit similar electrical properties (i.e. transconductance, current gain, and drain capacitance).
	10	14	Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2) The objective of this paper is to illustrate congestion, shorts, and practical approaches to fix both issues at lower/higher technology nodes. This paper also includes PnR tool (ICC2) related commands and their uses to overcome the mentioned issues.
	11	15	I2C Interface Timing Specifications and Constraints This paper covers the timing specification of I2C (Inter-Integrated Circuit) bus protocol. We have described all the timing specifications and how they are achieved by constraining our design. This paper focuses on the timing constraints for fast mode plus (The data transfer rate is 1 Mbit/s).
	12	7	Synthesis Methodology & Netlist Qualification The main objective of this article is to explain synthesis flow and post-synthesis netlist quality checks. In ASIC flow, synthesis is the part of the front-end design, while the back-end design takes the synthesized netlist as an input. So, the synthesized netlist should meet all netlist quality checks to reduce multiple iterations, which reduces the turnaround time and efforts.
	13	19	Layout versus Schematic (LVS) Debug In ASIC physical implementation, once layout is generated, it must follow all the design rules for successful manufacturing and must match the schematic of the required design. To ensure this in physical verification, Design Rule Check (DRC) is carried out to check whether the layout follows the rules for fault-less manufacturing or not.
	14	16	Demystifying MIPI C-PHY / DPHY Subsystem The newest member of the MIPI® PHY family, the C-PHY, arrived in October 2014 to a mixture of excitement and apprehension. How would this new C-PHY compare to the MIPI D-PHY and M-PHY®? What would differentiate the C-PHY, and would it be compatible enough with the D-PHY so that both could coexist in a hybrid subsystem? Now, years later, the answers are clear.
	15	New!!!	Floorplan Guidelines for Sub-Micron Technology Node for Networking Chips Overall, floorplanning is an important stage in physical design because it directly impacts the performance, power consumption, and area utilization of the final chip. A well-executed floorplan can significantly reduce design iterations and shorten time-to-market, making it an essential step in the chip design process.
	16	10	Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution Formal verification techniques have been developed using mathematical proof rather than simulation or test vectors to provide a higher level of verification confidence on properties. For example, the implementation can be either a Verilog RTL module or an abstract version of a particular design, while the specification is typically a set of properties that needs to be verified and expressed suitably. So, formal verification provides a complete verification of each specification property under considering corner cases even without test vectors.
	17	New!!!	Interface Timing Challenges and Solutions at Block Level In this article, we will address the challenges faced while fixing the interface timing and the solutions to overcome these challenges. We have used Cadence Innovus as our PnR and Synopsys Primetime as our Sign-off timing tool.
	18	6	Understanding Shmoo Plots and Various Terminology of Testers Nowadays, engineers are focusing more on testing, as device size/logic is becoming large. The designs are becoming complex with time and thus testing is becoming challenging in terms of time and cost both. To cater good yield, different test and vectors are provided by DFT engineers.
	19	New!!!	Antenna Effect in 16nm Technology Node This paper describes the antenna effect observed in the 16nm design and the way to identify antenna violations in design using different PV tool. We have described three different methods to fix the violations.
	20	20	Usage of Multibit Flip-Flop and its Challenges in ASIC Physical Design The continuous need for reduced size of the chip in the VLSI industry brings exciting challenges to the layout engineers for designing better and high-performing integrated circuits, which needs to consume low power even while reducing the silicon area and cost involved. Internal power is a component of the total power consumed by the chip, which is becoming more challenging to handle with the shrinking technology nodes.

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