Jul. 21, 2014 - Hierarchical test methodologies are being broadly adopted for large designs. They provide roughly an order of magnitude better ATPG (automatic test program generation) run time, reduce workstation memory requirements, and put the ATPG process much earlier in the design cycle than other methods. In hierarchial ...

Jul. 15, 2014 - This article describes three different clock domain crossing (CDC) verification methodologies and how they can best be used in verifying SoCs being designed today. Growing design size, proliferation of internal and external protocols, and aggressive power requirements are driving an explosion in the ...

Apr. 14, 2014 - This paper provides insight into a novel solution used to build SoCs targeting increased productivity in a complex environment. It describes the IP exchange and checking infrastructure deployed in a live design environment to ensure a well-timed and transparent transference of the sub-systems from the ...

Mar. 24, 2014 - This paper proposes a novel Test-Case methodology for System on chip (SoC) Verification in order to achieve high levels of reusability. It surveys the challenges of a traditional SoC Test-Case Methodology and then proposes a solution.

Mar. 17, 2014 - A metadata driven methodology allows automatic generation of netlists and design IP skeletons from a central database that contains registers, ports, interfaces, and other common design data. IP-XACT is commonly used to store the metadata. This paper explores how to use IP-XACT to represent the necessary ...

Mar. 10, 2014 - This paper describes an efficient, forward-looking architecture that enables handling of various form factors of LTE base stations with minimal software modification and without architecture changes. The architecture proposed allows easy migration to the next generation SoCs as well as to more powerful ...

Mar. 04, 2014 -

Feb. 20, 2014 - In this column, I'd like to introduce a novel technique for Intellectual Property (IP) and FPGA/ASIC clock domain crossing (CDC) analysis using a Grey Cell methodology rather than the traditional Black Box methodology.

Oct. 07, 2013 -

Sep. 09, 2013 - Post Silicon Validation is a vital phase of verification that deals with verification after the real silicon is in place. This paper revolves round the functional testing aspect of this phase. It starts with the basic theory about how a simulation output is converted to a different format so that the ...

Aug. 22, 2013 - Here’s a look at what’s new in test automation in terms of making blocks independently testable in design-for-test (DFT) approaches.

Jul. 15, 2013 - In this paper we first give an overview of agile development and discuss the advantages that software developers report from deploying an agile development methodology as well as the potential pitfalls. We then describe the author’s experiences of applying agile development techniques for hardware ...

Jun. 17, 2013 - Design for testability (DFT) and low power issues are very much related with each other. In this paper power reduction methodologies are discussed for a given design. Power management circuitries are developed to reduce functional power of the design. Power aware Scan Chains are implemented to create ...

Jun. 10, 2013 - This paper talks about the various challenges in validation of communication protocols. It then proposes a novel approach to ensure complete coverage thus delivering a robust IP.

Jun. 03, 2013 - With increasing complexities in power architecture and complex power domain partitioning, it is becoming imperative to drive functional and physical verification of these complex power logic hand in hand. However, despite relentless efforts of verification engineers, some issues may still skip through ...

Apr. 29, 2013 - As the mobile development cycles keep shrinking, innovative companies are using a number of strategies to balance complexity of software development with aggressive schedules. Starting software development early and getting to market early is one of the strategies that innovative mobile software developers ...

Feb. 04, 2013 - 3rd Party IP has become a buzz word since the Semiconductor industry has shifted gears to Fab-lite and eventually to Design-lite models in last few years. The new business models have opened the doors in many companies to overcome some of the internal weakness about possessing any IPs/design competencies ...

Jan. 28, 2013 - This paper describes how a reference verification platform built with the Discovery VIP for the AMBA ACE protocol can be utilized to accelerate the verification of multi-core SoCs. Also highlighted are Synopsys verification technologies like Discovery Visualization Environment (DVE) and Protocol Analyzer ...

Jan. 22, 2013 - Portable medical electronics has seen tremendous growth and adoption in the recent years. More equipment variants are being introduced in the market by an increasing number of companies. The need of the hour is better mass producible designs which are low in complexity and provide acceptable performance ...

Jan. 07, 2013 - In this article, we will discuss, in general, the ESL to RTL low power design flow, and then share the results of two case studies using real customer designs to evaluate the efficacy of a unique solution for ESL synthesis and power architecting.

Dec. 10, 2012 - In this paper, we outline the various parameters that affect the memory sub-system performance and also introduce the Sensitivity Analysis and Feature Exploration methodologies to analyze the degree of impact of each of these parameters. This platform, when used at an early architectural exploration ...

Oct. 22, 2012 - Evolution of technology conforming to Moore’s law has enabled packing of billion transistors on a single chip. This evolution in HW manufacturing processes has also changed the basic premise on which architecture’s were conceived in previous generation of chips.

Aug. 23, 2012 -

Aug. 06, 2012 - This article describes the factors which a designer should consider while defining clock tree architecture. It presents some real design examples that illustrate how current EDA tools or conventional methodologies to design clock trees are not sufficient in all cases. A designer has to understanding ...

Jul. 30, 2012 - This paper describes the causes of yield drop out in deep submicron technologies and methods to improve yield at design and manufacturing stage of IC development cycle.

Jul. 02, 2012 - There is much excitement about the semiconductor industry moving to 28nm and 20nm process technology. For a majority of products, however, it will be several years before these leading-edge process technologies make economic sense. These products will remain on mature process technologies, getting none ...

Jun. 11, 2012 - If the IC design trends of the past 20 years serve as an example, we will likely be required to implement a trillion transistors or more on a chip in the next 10 years. Even at 20nm, chip sizes touching billions of transistors present the age old, perpetually unanswered problem of how to most efficiently ...

May. 10, 2012 - Whether you are migrating to 20nm processes, considering the migration, or just watching the fireworks, you no doubt understand that there are profound issues to consider for physical design and implementation.

May. 07, 2012 - This paper discusses the relative merits of the various digital signal processing techniques used to channelise signals. ChannelCore Flex (CCF) exploits all of these strengths to provide a flexible channeliser architecture that is capable of supporting thousands of independently defined channels in ...

May. 07, 2012 - In the past, preparing a first implementation of an FPGA design on the board was relatively straightforward, requiring only a single design project, a handful of source projects, and a single design engineer. Subsequent improvements to the FPGA design on the board could be reflected in a matter of hours. ...

Apr. 16, 2012 - This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel ...

Mar. 19, 2012 - As the size of the SoC grows, virtual platform might comprise 3rd party components simulated with different methodologies. Co-Simulation comes in place, where components are simulated with various tools running simultaneously. These components exchange information in time steps and control signals. ...

Mar. 12, 2012 - This article reviews the history of key advances in ICs and EDA tools. The common theme presented in this article for the driver of technology innovation is the requirement to develop the most advanced microprocessor possible. Today, a low-cost, high-value-added business model can efficiently serve ...

Feb. 27, 2012 - This paper presents some key concepts necessary to design and build high-quality, mixed-signal IP in 28-nm or smaller geometries. The paper addresses specific design, layout, and verification techniques to address challenges posed in 28-nm technology nodes. Specifically, the paper focuses on three main ...

Feb. 22, 2012 - Today’s SoC verification environments require a reusable verification IP (VIP) infrastructure that allows plug-and-play of verification IP in SoC integration. The VIP must include hooks in the verification IP that would make writing an SoC integration test environment (tests, BFMs, monitors, checkers) ...

Feb. 14, 2012 - Two power formats, the same in every intent, but different in every detail. The differences go beyond syntax or even semantics; some differences are actually inherent in methodology…

Feb. 06, 2012 - SystemC Modelling is an emerging technology used for SoC Verification and termed as Virtual Platforms. This paper presents a systematic approach of converting a hardware algorithm into a functional timed SystemC model and simulation speed improvement techniques that could be incorporated.

Jan. 30, 2012 - This paper discusses various disadvantages of methodologies currently in use. Also in this paper there is description of methodology/flow which will help to achieve complete functional verification for Analog Mixed Signal Design/SoC’s. It also provides good confidence about functional verification ...

Jan. 16, 2012 - This paper will summarize previous work about SystemVerilog UVM transaction recording, transaction modeling and the supporting transaction recording APIs. This discussion will span a wide spectrum, from simple concepts such as transaction begin and transaction end, to more advanced concepts such as ...

Jan. 03, 2012 - This paper presents functional coverage analysis automation and an approach to scale down overall simulation time. It is well known that functional verification of configurable IP cores is a real challenging task in any digital design development. Consequently, it is necessary to develop new methodologies ...