Aug. 31, 2023 - In this article, we will explore the concept of design verification, its importance, the process involved, the languages and methodologies used, and the future prospects of this critical phase in the development of VLSI design.

Aug. 22, 2022 - In this article, let me walk you through various verification methodologies we use for verifying IPs, Sub-systems, and SoCs and explain why we need new methodologies/standards like PSS.

Mar. 17, 2016 - The IoT sensor backplane is increasingly expected to monitor the system under test on a real-time basis. This is true for IoT sensor solutions monitoring body area networks, safety and security solutions, industrial factory and process automation solutions, and building automation solutions to name ...

Jun. 16, 2014 - IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, quality and maintainability of the translated code. VHDL and SystemC are frequently co-simulated by ...

Jun. 02, 2011 - ASIC vendor eASIC's announcement of a conversion path from their Nextreme structured devices to a fully cell-based ASIC offers an interesting opportunity to reflect on conversion methodologies. Comparing it to a recent discussion of the KaiSemi conversion flow, which takes a design from an FPGA to a ...

Jan. 04, 2011 - Designs must be developed using techniques that will specifically enable mission- and safety-critical operation of the design after it is deployed. For example, EDA tools must allow engineers to build and retain redundancy in the design, as well as custom error detection and mitigation logic that automatically ...

Aug. 13, 2009 - Synopsys provides an interesting design article on how to improve the your electrical system and power management in vehicle design by using the virtual vehicle concept and simulation-based development methodologies.

Jul. 29, 2009 - Systems and semiconductor suppliers are increasingly looking at methodology changes that can help accelerate assembly of chips and systems through one or multiple forms of automation. Why?

Apr. 27, 2009 - Increasing complexities of the programmable components demand newer modeling methodologies. Architects need to evaluate various design constraints in a short time and also generate tools for the new architecture. Although SoC and processor modeling has been around for a long time, newer methodologies ...

Jan. 12, 2009 - The demand to meet multiple, sometimes conflicting, constraints means it's a wonder that FPGA and PCB designers aren't fitted for straightjackets by the time the board finally tapes out. This article explores the tools, techniques, and problems that designers struggle with when developing FPGA-based ...

Jun. 02, 2008 - Engineers must leverage design insights to be able to develop intelligent verification methods.

Aug. 14, 2007 - The verification of IP cores continues getting more complex and time consuming, especially processor cores, such as CPUs, floating-point units, and digital signal processors, the subject of this story. The challenge is to design and verify a new embedded vector processor with significant enhancements ...

Sep. 21, 2006 - ESL is emerging as viable – indeed necessary – part of the SoC design process. The viability is being driven by the emergence and adoption of industry-wide standards.

Nov. 21, 2005 - Let’s have a look at the prototype place in the development flows.

May. 26, 2005 - by Samuel Picchiottino, Mario Diaz–Nava*, Benoit Foret, Sylvain Engels, Robin Wilson from STMicroelectronics, Crolles, France -- *STMicroelectronics, Grenoble, France

Jul. 30, 2004 - Advantages of FPGA design methodologies

Dec. 19, 2003 - System Design Methodologies for System on Chip and Embedded Systems

Dec. 14, 2023 - In this article, we dissect the significance of QA in embedded systems, where precision and reliability are not just desired but mandatory. Join us as we navigate through various aspects of QA, exploring how QA shapes the robust functionality of embedded systems.

Aug. 21, 2023 - This article delves into the significance of different prerequisites of physical design in VLSI, highlighting its multifaceted importance and the intricacies of the process.

Jul. 21, 2023 - My recent article, ‘Chip War without Soldiers’ explained the importance of upskilling and preparing the chip design workforce in this current scenario, and it also explained how it will lead to ‘Fabs without Chips’ if we don’t prioritize it. VLSI Engineers are the pillars of the semiconductor ...

Jul. 11, 2023 - Several factors have influenced the evolution of VLSI technology, including advances in semiconductor materials and manufacturing processes, the development of computer-aided design (CAD) tools, and the growing demand for high-performance electronic systems which includes VLSI design and verification ...

Feb. 24, 2023 - In this open era of computing, RISC-V community members are ambitious to create various kinds of RISC processors using RISC-V open ISA. However, the risk of using RISC-V ISA is higher because the proven processor verification flow is still proprietary to established processor fabless IP companies and ...

Jan. 30, 2023 - Even as software algorithms that mimic human thoughts and ideas are the foundation of AI, hardware is also an important component this is where the role of Field Programmable Gate Arrays (FPGAs) and Graphics Processing Units play a vital role.

Nov. 16, 2022 - Processor verification, however, is never trivial but requires combining the strengths of multiple verification techniques. This technical paper considers how to efficiently verify a RISC-V processor using a multi-layered approach known as the Swiss cheese model adapted from the world of avionics.

Aug. 01, 2022 - This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all ...

Jun. 27, 2022 - This article gives the procedure or step-by-step guide to integrating the C model in the UVM Testbench/environment using the SystemVerilog DPI (Direct Programming Interface) feature.

Jan. 13, 2022 - Harmony Trace is an enterprise level server-based application with a web-based UI that interfaces to your existing requirements, EDA tool, documentation, and support systems, creating a system-of-systems that allows complete visibility of requirements traceability through the entire SoC design flow ...

Dec. 22, 2021 - The goal of this article is to walk through what is SOM (system on module), which all are available most commonly SOM today in the market, and the benefits of uses.

Dec. 20, 2021 - Recent Integrated Circuits (ICs) are moving towards the goal of high performance and low power. At the same time, it makes the ICs very complex and has certain specific requirements for superior performance. One of the tasks is the custom routing of power and other nets that cannot be implemented with ...

Aug. 30, 2021 - As the semiconductor industry is prominently marching into the nanometer era, fundamental elements face their physical limits significantly, such as electric field across gate dielectric layers, leakage from an ultra-short channel or steep doping profile, newly incorporated leakage/current models, etc. ...

Jun. 24, 2021 - In this article, we have discussed about the structure of the ADAS Model which we have created by using VisualSim software. The model is built with 4 raders, 6 cameras, and 2 Lidars connected to 12 ECUs, gateways and IEE802.1Q networks. The prototype is set up to quickly modify feature packages and ...

Jan. 18, 2021 - As technology advance, we see complex SoCs emerging in the market with multiple interfaces. These complex SoCs can have multiple clocks driving multiple modules, which may be getting divided further to generate new clocks in the chip and so the complexity increases.

Nov. 12, 2020 - Semiengineering.com recently reported on an industry survey showing an increase in respins due to analog circuitry failing or falling out of operable range.

Jun. 08, 2020 - The free lunch offered for decades by Moore’s law is now over and scaling down to the next technology node no longer offers the required energy efficiency gains. Design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the demands of the new IoT ...

May. 04, 2020 - Currently, there is a strong belief among the cyber security experts that hardware security is imperative since it is more efficient, effective, reliable and tamper-resistant than software security. As a matter of fact, providing trusted execution environment (TEE) and embedding a hardware root of trust ...

Mar. 16, 2020 - The purpose of this article is to highlight the different methodologies to reduce power consumption during ASIC manufacture testing. It distinguishes the different architectures & methodologies to optimize power consumption during a test mode of the design with implementation. There are number of techniques ...

Jan. 06, 2020 - Nowadays, engineers are focusing more on testing, as device size/logic is becoming large. The designs are becoming complex with time and thus testing is becoming challenging in terms of time and cost both. To cater good yield, different test and vectors are provided by DFT engineers.

Dec. 11, 2019 - Changing your methods of performing verification can reduce verification time by several weeks.

Oct. 03, 2019 - This paper introduces an emerging new standard called IP Security Assurance (IPSA) to address these concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to highlight IP assets and associated entries in the Common IP Security Concerns ...

Jul. 22, 2019 - At BitSim, we have a way to simplify and speed up the development cycle. In this document, we will discuss the issue of network load in an IoT environment as well as "our" way to speed up the development.