TLM Peripheral Modeling for Platform-Driven ESL Design Using the SystemC Modeling Library
by Tim Kogel, CoWare Inc., Solution Specialist
Abstract
This article provides an overview of a SystemC-based Transaction Level Modeling (TLM) methodology for the rapid creation of SoC platform models. First a brief overview of the ESL design tasks and the corresponding modeling requirements is given. The main topic is a methodology for the efficient creation of transaction-level peripheral models. Those are usually specific for a particular SoC platform and have to be created by the ESL user.
Click here to access this paper (PDF file)
Related Articles
- Step Up to C for Embedded R&D
- Methodology for Rapid Development of Loosely Timed and Approximately Timed TLM Peripherals
- SystemC: Key modeling concepts besides TLM to boost your simulation performance
- Design & Verify Virtual Platform with reusable TLM 2.0
- Using IP-XACT Metadata for a TLM Modeling Flow
New Articles
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |