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5V Library for Generic I/O and ESD Applications TSMC 12nm FFC/FFC+ process.

• Targets up to 8A applications
• >8kV HBM
• Silicon Proven

8Kx8 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V Logic/BCD Process

• Fully compatible with MXIC 0.18µm BCD process
• High capacity: 64 kbits OTP macro
• Low voltage: 1.8 V ± 10% read and 3.70 V ± 5% program

12-bit, 5 GSPS ADC on GF 22FDX

• 12 bit resolution
• 5 GSPS sampling rate
• 6 GHz Input Bandwidth

DiFi IP core

• Supports: Signal Data, Flow Control, Signal and Version Context Packets
• Integrates Easily with UDP/IP Ethernet Stack through the AXI interface

Special Purpose Low (Statistical) offset Operation Amplifier

• Power Supply : 1.8 V
• Open loop gain : 109 dB
• PSRR : 98 dB@ 1 KHz

PCIe 6.0 PHY IP for TSMC N4P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization

High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X

• Supports up to 9.6 Gbps/pin
• Supports 16 channels (32 pseudo channels)
• Supports AXI4 mainband and AXI4-Lite sideband interfaces

General Purpose Neural Processing Unit (NPU)

• Hybrid Von Neuman + 2D SIMD matrix architecture
• 64b Instruction word, single instruction issue per clock

Dilithium IP Core

• Supports sign and verify operations.
• Supports all three Dilithium modes.
• Has fully stallable input and output interfaces.

8-bit/12-bit JPEG Codec IP upto 64Kx64K

• Compliant with the Extended sequential DCT mode of ISO/IEC 10918-1 JPEG standard, the WAVEJ can also support motion JPEG streams with varied color formats supporting resolutions up to 64K x 64K.

112G Ethernet PHY IP LR-Max for TSMC N4P

• Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)

PCIe GEN6 PHY

• Supports PRBS (Pseudo Random Binary Sequence) testing including loopback modes

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

Die-to-Die PHY

• 64 data lanes with configuration and bump map layout dependent on the PHY type (UCIe, BoW, UMI, SBD)

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X

• Complete, integrated LPDDR5X/5/4X solution from a single vendor when combined with Synopsys’ LPDDR5X/5/4X PHY IP

UCIe D2D Adapter

• Ultra Low Latency
• CRC and Retry, or Parity Computation
• Multiple Protocols,

UCIe PHY & D2D Adapter

• 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
• UCIe v1.1 specification

Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more

AV1/HEVC/AVC/VP9 Video Codec HW IP 8K30fps@550MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

RT-7xx CryptoManager Root of Trust

• Secure co-processor
• Main processor agnostic
• Standard secure applications

32G Multi Rate SerDes PHY - GlobalFoundries 22FDX

• Line rates from 1.25 up to 32Gbps
• PCIe up to Gen4.0
• PIPE interface

UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect

• Emerging Standard Knowledge
• Flexibly Configurable
• Best in Class PPA

KYBER IP Core

• supports encapsulation and decapsulation operations
• supports all modes K=2,3,4.
• is compliant with Kyber specification round 3.