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8.5GHz Fractional-N/SSC PLL

• 4nm Low Power Plus (LN04LPP) CMOS device technology
• Dual power supply of 1.2V±10% and 0.85V+5% ~ 0.75V-10%
• Operating junction temperature(TJ): -40°C ~ 125°C

Camera 3DNR IP - AMUR (ME based)

• High Performance
• Strong on Ghost
• Optimized for Low-light Environment

Compact, low-power, 8bit ADC

• GF 22nm FDX
• High SFDR
• Compact

224G Ethernet PHY IP for TSMC N3P

• Supports full-duplex 1.25 to 224Gbps data rates
• Enables 200G, 400G, 800G, and 1.6T Ethernet
• Ethernet interconnects for wired network infrastructure

ARINC 429 IP

• Independent Receivers (Rx) with FIFO
• Independent Transmitter (Tx) with FIFO
• Number of RX and TX line defined by Generics

PVT - Process, Voltage, and Temperature Monitor with Interrupt 7nm/6nm

• ± 4C temperature accuracy without trim
• ± 1C temperature accuracy after single room temperature trim
• Voltage monitor supports both single-ended and differential inputs, with 4:1 input mux

40 mA LDO voltage regulator (3.3/5.0V to 1.8V)

• TSMC 180nm technology
• 1.8V output voltage
• Output voltage trimming

40G UCIe PHY IP on Samsung SF4X

• Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
• Compliant with the latest UCIe specification

Flipchip 5V Fail-Safe GPIO, 5V GPIO, 5V GPI and I2C Compliant 5V ODIO

• Fail-Safe Architecture
• Two different GPIO footprints.
• I2C Compliant ODIO

Highly Accurate RC Oscillator

• 33KHz highly regulated frequency
• -40°C to +125°C Operating Temperature Range
• ±2.5% accuracy over temperature ranging from -40o to 125oC.

DDR5 Temperature Sensor I3C / I2C

• Two wire bus serial interface
• Up to 12.5 MHz transfer rate
• Packet Error Check (PEC) Function

UniPro 1.6 Host/Device IP

• Compliant with MIPI Alliance UniPro Standard version 1.6 specification
• HS-G3 transmission in M-PHY

PCIe 6.2 Switch

• 1 upstream port, up to 7 downstream ports
• Up to 128 lanes
• Up to x16 link width per port

UCIe Die-to-Die Chiplet Controller

• AXI over UCIe Streaming Protocol
• Link Error Detection and Retry Feature
• APB for Controller Control

Multi-protocol SerDes PMA

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

DP/eDP1.4b RX PHY

MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP

• Compliant with MIPI D-PHY v2.5 and C-PHY v2.0 specifications
• Supports MIPI DSI and CSI-2 protocols
• Supports HS data rates up to 6.5Gbps (6.5Gsps) per lane (per trio)

PCIe 4.0 PHY on 5nm

• Low power consumption and small area
• Support 1-, 2- and 4- lane configurations
• Automatic built-in self-test (Loopback)

24-bit 19.2Ksps Analog front end (AFE) having sigma delta ADC for Industrial process control and low power sensors

• Ultra-low power delta sigma ADC
• High performance up-to 124dB dynamic range
• Industry best IP specifications

UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)

Low-Latency SerDes PMA

• Very wide CDR range - operates with data rates from 0.6Gbps to 4.0Gbps
• Compatible with JESD204A, JESD204B, OIF-CEI-6G-SR, CPRI, SGMII, XAUI and V-by-One

32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM

• 2 different packages with or without vector: A46MPV, A46MP
• in-order dual-issue 8-stage CPU core with up to 256-bit VLEN
• Symmetric multiprocessing up to 16 cores

Agile ECC/RSA Public Key Accelerator with 128-bit ALU

• Offloads computationally intensive parts of public key cryptography
• Support for Arm® AMBA® AHB™/AXI™ and synchronous RAM slave interfaces

TSMC CLN7FF 7nm Clock Generator PLL

• 800MHz-4000MHz
• Delivers optimal jitter performance over all multiplication settings.