English
You are here:
FEC Simulator
The ntFEC_SIM S/W module provides a user-friendly, intuitive graphical user interface that enables efficient bit-true simulation of a concatenated forward error correction system based on ntVIT (Viterbi decoder) and ntRS Viterbi (Reed Solomon codec) IP cores.
The ntFEC_SIM platform implements a complete transmission system comprised of the following modules:
Psuedo-random data generator.
Reed Solomon Encoder outer code (bit-true model of ntRSE core).
Convolutional encoder inner code.
BPSK, QPSK or Mary-QAM modulator.
AWGN channel with adjustable SNR level (bit-true model of ntAWGN core).
Viterbi Decoder inner code (bit-true model of ntVIT core).
Reed Solomon Decoder outer code (bit-true model of ntRSD core).
BER Counter.
The ntFEC_SIM platform implements a complete transmission system comprised of the following modules:
Psuedo-random data generator.
Reed Solomon Encoder outer code (bit-true model of ntRSE core).
Convolutional encoder inner code.
BPSK, QPSK or Mary-QAM modulator.
AWGN channel with adjustable SNR level (bit-true model of ntAWGN core).
Viterbi Decoder inner code (bit-true model of ntVIT core).
Reed Solomon Decoder outer code (bit-true model of ntRSD core).
BER Counter.
Features
- Efficient forward error correction simulation platform for Reed Solomon and Viterbi codes.
- Fully configurable Reed Solomon and Viterbi code parameters.
- Bit-true models.
- Flexible and easy to use configuration GUI.
- BER vs SNR, BLER vs SNR plots.
- BER/BLER measurements window.
- Configurable QAM modulation level.
- AWGN channel with configurable number of errors per SNR level.
- Internal random data generator, support for external user data input.
- Data files are generated at input/outputs of every block in the transmission path.
Deliverables
- Executable code
- Users Manual
View FEC Simulator full description to...
- see the entire FEC Simulator datasheet
- get in contact with FEC Simulator Supplier