400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Industry Expert Blogs
Open-Silicon adds Silicon Logic Engineering - for a good reasonPractical Chip Design - Brian BaileyJan. 13, 2010 |
SoC design practice has changed profoundly in recent years. While EDA vendors, IP suppliers, and the marketing departments at FPGA companies seem to think that every new SoC requires a $250 M start-from-zeros design effort, in fact SoC design has bifurcated into two distinct flows. One flow creates a platform design: a completely new SoC to serve a new application. That effort really does start from nearly scratch, and it requires an increasing wealth in people, time, and money. The other flow modifies the platform slightly to create a derivative design. The derivative flow exploits the platform as much as possible, sometimes just replacing one block in the physical design without changing the rest of the chip at all. Consequently, a derivative design may only require a dozen engineers and a couple of million dollars.
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