Industry Expert Blogs
Is 2D Scaling Dead? Looking at Transistor Designharry... the ASIC guy - Harry GriesJun. 23, 2010 |
In the last blog post, I started to examine the question “is 2D scaling really dead or just mostly dead?” I looked at the most challenging issue for 2D scaling, lithography. But even if we can draw the device patterns somehow on the wafer at smaller and smaller geometries, does not necessarily mean that the circuits will deliver the performance (speed, area, power) improvements that Moore’s Law has delivered in the past. Indeed, as transistors get smaller (gate length and width) they also get shorter (oxide thickness). There are limits to the improvements we can gain in power and speed. We’ll talk about those next.
Related Blogs
- Let's Talk PVT Monitoring: Thermal Issues Associated with Modern SoCs - How Hot is Hot?
- Moortec "Let's Talk PVT Monitoring" Series with CTO Oliver King
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Let's Talk PVT Monitoring: Understanding Your Chip's Age
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions