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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Industry Expert Blogs
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Scalable Architectures Expand into FPGAsJB's Circuit - John BlylerJun. 28, 2010 |
Moore’s Law assures us that the transistor count of IC devices like FPGAs, ASICs and ASSPs will double every two years – with each successive process node. This means that chip density or capacity will increase and power consumption per transistor will go down.
Still, the numbers for Xilinx’s upcoming 28nm Virtex-7 family of FPGAs are impressive: 50 percent power reduction and more than doubling of the logic cell density (now at 2 million) over its 40 nm Virtex 6 devices.
Aside from improved power, performance and device capacity, the new 7 Series FPGAs offers scalability across the full family of devices. In previous generation of FPGAs, scalability was limited to within a family of devices, such as within the 40nm Spartan or 45nm Virtex-6 families.
