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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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The Increasingly Hazardous World of FPGA VerificationFunctional Verification Blog - Tom Anderson, CadenceOct. 26, 2010 |
Last week saw the publication of two interesting blog posts regarding the growing challenges of FPGA verification, first from my buddy Dave Orecchio over at GateRocket and then from my Cadence colleague Steve Leibson. Both posts made the point that FPGA developers are increasingly facing the same verification issues as developers of non-programmable devices. This trend has been evident for quite a few years, but the number of FPGA users affected has grown from a tiny fraction to an entire upper tier of developers whose design size and complexity rival or even surpass many ASIC and SoC projects.
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