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ASIC and ASSP Prototypes Accelerate Below 65nmJB's Circuit - John BlylerJan. 14, 2011 |
One time-honored way to achieve the ever conflicting trade-off between high performance and low power is by manufacturing ASIC designs at a lower process node. This approach works especially well with digital circuits, which scale more easily to lower nodes than their analog brethren.
One indicator of this trend toward lower manufacturing geometries is the shrinkage of the process node of current and future FPGA-based ASIC prototypes. Designers use such hardware prototypes to architect and verify the newer or more troublesome portions of their latest leading-edge chip designs.
Currently, the trend is toward prototypes targeted at designs below 65nm (see Figure 1). This trend is hardly surprising. Early in 2010, Xilinx announced that their latest generation of FPGAs was manufactured at the 28nm process node. On the processor side, Intel recently announced the building of a new 22nm fab in Oregon.
