400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Industry Expert Blogs
3D chips: design toolsEDA Graffiti - Paul McLellanJan. 19, 2011 |
One of the open areas for 3D chip design is what the design methodology needs to be and what design tools will be required. A more fundamental issue is going to be the business model to pay for tool development. At least in the short term, only a few 3D designs are going to be done and so a conventional EDA “build the tools and wait for everyone to do 3D designs” is not going to work. In fact Antun Domic of Synopsys, presenting at the 3D conference, explicitly pointed this out: EDA works economically when a large number of people use the same methodology so that the methodology can be wrapped up in the tools and sold in volume. Wally Rhines at the EDAC CEO forecast meeting said the same thing: that if semiconductor vendors expected to get 3D tools without paying incrementally for them then it was unlikely to happen.