Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
The 3 Evils of Routing CongestionArteris Connected Blog - ArterisFeb. 07, 2011 |
Much of the talk today in the system on chip (SoC) ASIC business is about how smaller critical dimensions are driving the use of more and more IP blocks on a single SoC. As the number of IP blocks increases, the act of assembling and physically manufacturing the SoC become Herculean. What’s the big deal?
Would you believe, Routing Congestion!?
It sounds kind of obvious, but the more IP blocks you have that need to be connected, the more wires you need to connect them. What isn’t as obvious is that routing congestion has 3 evil effects:
1. Poor performance
2. Longer, more uncertain schedules
3. Lower yields and higher costs
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