55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish LineLogic Design - Kenneth ChangFeb. 08, 2011 |
Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs, whether they are related to bug fixes (those 'oh oh' moments of silence), or intended functional changes (which are not out of the ordinary -- maybe your marketing department has requested the design team to add a new feature to the ASIC because of competitive pressures). Thus, planning for ECOs is a necessity for any solid ASIC flow.
Let's take a step back. If you are unaware of what the term "ECO" means, in the ASIC world, it is defined as the "Engineering Change Order". In simple terms, it is a change to your design, whether it be functional, timing, or electrically related. In our case we are going to focus on functional logic design changes, since it is historically a big challenge to make them predictable, according to customer experiences. By the way, ECO is an acronym widely known and used because it is that common (and painful). ECOs hurt by reducing overall team productivity if not planned for carefully.
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