Industry Expert Blogs

Xilinx has acquired high-level synthesis start-up AutoESL Design Technologies, bringing the AutoPilot high-level-synthesis tool in-house. AutoPilot accepts a C, C++, or SystemC description of the functionality of an algorithm or task and generates a register-transfer-level (RTL) implementation in Verilog or VHDL.  The RTL implementation is then processed through the traditional FPGA RTL logic synthesis, place-and-route, and verification tool flow. Like other high-level synthesis tools, AutoPilot offers time savings in the RTL design and coding process, and speeds the verification process by enabling much of the verification work to be done at the C, C++, or SystemC level, where simulations are dramatically faster than those at the register or gate level.

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