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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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Microprocessor Report publishes extremely interesting comparison of STMicroelectronics SPEAr-1300 and Xilinx Zynq ARM-based, dual core application processorsEDA360 Insider - Steve LeibsonJun. 16, 2011 |
Last month, STMicroelectronics introduced the latest in its line of SPEAr (Structured Processor Enhanced Architecture) application processors and Microprocessor Report has just published a very interesting article about the new products (paid subscription required). The SPEAr-1300 series is based on two 600MHz ARM Cortex-A9 microprocessor cores (upgraded from the 333MHz ARM9 cores used in the earlier SPEAr parts). Each ARM processor core in the SPEAr-1300 embedded application processor has two 32-kbyte L1 caches and the two processor cores share a 512-kbyte L2 cache. The SPEAr-1300 application processor also includes a number of hard-core IP peripherals including a Gigabit Ethernet port, a PCIe/SATA port, and two USB 2.0 ports. In addition, there are 1.3 million uncommitted ASIC gates that can be configured for specific applications and, in a throwback to the disco days of the 1980s, these ASIC gates are configured as a metal-defined gate array so the wafers can be stockpiled awaiting final metal designs.
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