English
Industry Expert Blogs
|
Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)Cadence IP Blog - Jacek DudaJul. 28, 2011 |
This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.
Related Blogs
- Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features
- PCI-SIG DevCon 2013: M-PCIe with M-PHY Shifts into GEAR 3
- Rambus Demonstrates Advancing Data Center Capabilities with CXL Over Optics
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops