English
Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
|
17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction Design and Verification?Cadence Blog - Jack EricksonOct. 05, 2011 |
In their presentation at the recent SystemC Japan conference, Renesas Micro Systems, Inc. (RMS) stated 2 SystemC "beginners" completed a 17M gate design in 8 months, achieving first-pass timing closure at 650 MHz targeting 40nm.
Two thoughts came to my mind:
- Wow!
- What is their ROI of migrating from an RTL-driven methodology to a SystemC-driven methodology?
