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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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Arteris vs Sonics battle...Let's talk NoC architectureSemiWiki - Eric EsteveNov. 04, 2011 |
The Network on Chip is a pretty recent concept. Let’s try to understand how it works. Anybody who has been involved in the Supercomputer design (like I was in the 80’s), knows that you need a “piece” between the multiple CPU and memory banks, at that time a “crossbar switch”. To make it outrageously simple, you want to interconnect the M blocks on the left side with the N blocks on the right side, to do so you create a switch made of MxN wires.
