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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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Formally verifying protocolsSemiWiki - Paul McLellanNov. 16, 2011 |
I attended much of the Jasper users' group a week ago. There were several interesting presentations that I can't just blog about because companies are shy, and some that would only be of interest if you were a user of Jasper's products on a daily basis.
But for me the most interesting presentations were several on an area that I didn't realize this sort of formal verification was being used for. The big driver is that modern multi-core processors now require much more sophisticated cache control than before. ARM in particular has created some quite sophisticated protocols under the AMBA4 umbrella that they announced at DAC.
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