Aeonic Generate Digital PLL for multi-instance, core logic clocking
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System-Level Design and the Waves of EDACadence Blog - Frank SchirrmeisterJan. 31, 2012 |
Before January comes to an end it is time for my annual flashback and brief reflection on where we are in system-level design, and a look at how the state of today compares to the predictions we made 10 years ago.
2011 was an interesting year for system-level design. In May Cadence announced its participation in the system-level domain with the System Development Suite. The year before, in 2010, we had seen consolidation in the virtual platform space with Synopsys picking up VaST, CoWare and Synfora. Later in 2011 we saw Mentor spinning out their high-level synthesis technology to Calypto. Overall, system-level design is a topic covered by all major vendors and not a forte of visionary start-ups anymore.
This year, when digging up the January IEEE Spectrum collection from my garage, I found issues from both 10 years and 15 years ago, 2002 and 1997. Ouch. 1997 was the year when I moved to the U.S. leaving active software and chip development behind, joining Cadence in technical marketing ... I have been in system-level design for 15 years. Time for a check point.