55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Industry Expert Blogs
Breaking Down the "Make vs. Buy" Barriers for IPSonics, The Official Blog - Jack Browne, Sr. VP Sales, Marketing, SonicsFeb. 27, 2012 |
As the fabless era disaggregated EDA and IP offerings, there are areas where in- house development is still the norm, even with today’s $2.5B IP industry. One of these is on-chip network – connecting the IP cores and memory subsystem.
On-chip interconnect or networks-on-chip (NoCs), in many companies, is still regarded as a part of the IP that can be internally developed for SoCs. With deeper process nodes, such as 28nm, enabling device convergence, more cores are included in the SoC, accelerated further by subsystems.
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