55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Industry Expert Blogs
Low-Power Design: Is the Problem Solved?EDA360 Insider - Steve LeibsonApr. 12, 2012 |
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your expectation is that the phone might go for a day before needing a recharge.” Why? Because we understand that the phone is now doing a lot more than it once did, said Wang as he entered into the main part of his talk.
We’d like to think that achieving closure on power-consumption goals during the design process is smooth and deterministic. The idealized work curve looks something like this in our heads:
Related Blogs
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Obsolete & EOL Parts
- Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing
- Digitizing Data Using Optical Character Recognition (OCR)