MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
The Facts: Why Accelerated VIP Is Needed for SoC VerificationFunctional Verification Blog - Peter HellerMay. 15, 2012 |
On Tuesday May 15th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question. This blog will answer that and explain the rationale behind Cadence's AVIP and more about our products and plans going forward.
A key driving factor impacting verification approach is the size of the design. Today designs commonly are in the 10's and even 100's of millions of gates. And software size is growing at an even faster pace. There's no respite in sight for these torrid growth rates. So even if you don't face such verification challenges immediately, read on, because they're coming.
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