MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
DFI's Impact On Smart Phones, CloudThe Eyes Have it : A Mixed-signal IP Blog - Navraj Nandra, SynopsysJun. 11, 2012 |
In the world of chips that connect to external memories, which is most chips for smart phones and data centers that manage the cloud, by the way; DFI defines the interface protocol “the lingo” as it were, between the memory controller logic and the physical (PHY) interface. The DDR PHY interfaces to an external memory. And what the industry is gearing up for is that external memories will be called LPDDR3 (lower power and fast – think mobile phone and video stream) and DDR4 (fast and well, just fast – think iCloud data center).
The point of DFI is that it reduces the integration time between the memory controller logic and the PHY. Reduces hook-up errors; basically. Two major updates to the DFI specification were recently announced that includes support for LPDDR3 and DDR4 – essentially to address the upcoming lower power and higher speed DRAM’s respectively. From a technical perspective the updates are listed below: