1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
Industry Expert Blogs
3D and power is all wetPractical Chip Design - Brian BaileyJul. 23, 2012 |
There has been a lot of talk recently about 3D ICs and the challenges associated with them. One area that contains some of the biggest challenges is related to power – how do you get power in and how do you get the heat generated back out again. To understand this a little more, I talked to Madhavan Swaminathan who is the Joseph M. Pettit Professor in Electronics at the School of Electrical and Computer Engineering and Director of the Interconnect and Packaging Center (IPC), an SRC Center of Excellence, at Georgia Tech, Atlanta. He is also the Founder and CTO of E-System Design.
I featured the introductory chapter of his book “Power Integrity Modeling and Design for Semiconductors and Systems” during my EDA Designline series about power in April. This book chapter provides a good background into the power delivery network and its analysis.
Related Blogs
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Let's Talk PVT Monitoring: Thermal Issues Associated with Modern SoCs - How Hot is Hot?
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing
- Let's Talk PVT Monitoring: Understanding Your Chip's Age