400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Industry Expert Blogs
Enhancing your MIPI LLI UnderstandingVIP Central - Parag GoelSep. 05, 2012 |
Before starting work on any of the MIPI Alliance protocols, I was told that it has become the fastest growing interface technology, usurping long established technologies like Ethernet, USB, and PCIe . Being assigned the responsibility of architecting a Low Latency Interface (LLI) Verification IP, I jumped straight in with great enthusiasm. As I went feature by feature through the implementation I found that a few features were left to the implementer’s choice. I aim to share few of my experiences on certain features during the course of the development.
Related Blogs
- Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing
- Why, How and What of Custom SoCs
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets