Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
What Does it Take to Migrate from e to UVMe?Functional Verification Blog - Team SpecmanSep. 06, 2012 |
So you are developing your verification environment in e, and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate from e to UVM e?"
Well, this is a bit of a trick question. The short answer is that if you've adopted eRM in the past, migration to UVM e will only take a few minutes. If your environment is not eRM-compliant, it will take you longer.
And now to the details. What exactly is UVM e, in comparison to native e (IEEE 1647), and to eRM? What is in UVM? And what's all the fuss about?
Related Blogs
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- ARM vs RISC-V: Beginning of a new era
- Let's Talk PVT Monitoring: Thermal Issues Associated with Modern SoCs - How Hot is Hot?
- Arm and Arteris Drive Innovation in Automotive SoCs