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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
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Feasability of 28 nm Process Is IncreasingGabe on EDA - Gabe MorettiSep. 10, 2012 |
A couple of recent press releases from both Cadence and Synopsys provided information that widens the usability of the 28 nm process to a larger segment of system companies. First Cadence announced success in using its DDR4 design IP in TSMC 28HP and 28HPM processes. Shortly after ward Synopsys wrote that its 28 nm DesignWare IP had been successfully used in more than 30 test chips for the 28 nm process.
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