English
Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
|
TSMC dilemma: Cadence, Mentor or Synopsys?SemiWiki - Eric EsteveOct. 18, 2012 |
Looking at the Press Release (PR) flow, it was interesting to see how TSMC has solved a communication dilemma. At first, let’s precise that #1 Silicon foundry has to work with each of the big three EDA companies. As a foundry, you don’t want to lose any customer, and then you support every major design flow. Choosing another strategy would be stupid.
