MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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What a large ASIC should look like in a couple of yearsPackage Matters - Javier DeLaCruzOct. 30, 2012 |
… and it looks nothing like today’s large ASICs
The current state of the art
For years, large ASICs like the ones used in network processing, supercomputing and high-end personal computing have had very interesting similarities. The figure below is a fairly typical floorplan of such an ASIC. After taping out over a dozen of these types of chips a year, it is interesting to see that the interfaces have changed, processors are faster and memory data rates have increased, but the basic floorplan remains similar.