English
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
|
Wafer Costs: Out of Control or Not?SemiWiki - Paul McLellanDec. 31, 2012 |
I didn't attend the International Electronic Device Meeting (IEDM) earlier this month, but there have been a lot of reports on the inter webs especially about 20nm and 14nm processes. Some of this is really geeky stuff but I think that perhaps the most interesting thing I've read about is summarized in this chart:
Related Blogs
- Let's Talk PVT Monitoring: Thermal Issues Associated with Modern SoCs - How Hot is Hot?
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Let's Talk PVT Monitoring: Understanding Your Chip's Age
- Moortec "Let's Talk PVT Monitoring" Series with CTO Oliver King
- Digitizing Data Using Optical Character Recognition (OCR)