English
55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Industry Expert Blogs
|
Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantageSemiWiki - Eric EsteveJan. 18, 2013 |
We all know the concept of “one stop shop”, becoming popular in the Design IP market. The topic we will address today is NOT the “one stop shop”, even if it looks similar, but rather that we could call “consistent design flow”.
What does that means? Simply that, if your SoC design is integrating a DDRn (LPDDR2, DDR3 or even DDR4, let’s say DDR3 in this case) Memory Controller, you will have to run functional simulations of your SoC behavior, being as close as possible of the real life, then these simulations should integrate accurate model of the DDR3 memory chip. The easiest and safest path is to acquire this model. Denali has been started in the mid 90’s with this primary charter, develop and sale Memory Models. Nobody ignore that Denali has been acquired in 2010 by cadence (for a record $315M, or about 7X the 2009 company revenue!), and that Denali’s port-folio was based on: Verification IP (for Interface IP like PCIe, USB and so on), DDRn Memory Controller IP and… the Memory Models.
Search Verification IP
1,000 Verification IPs from 50 Vendors
Example: Memory Model Verification IPs