English
Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
|
A Simple Method for Choosing a Chip Design CompanyAnySiliconFeb. 25, 2013 |
In 2005 I applied for a job in Singapore. The job required some technical and business skills and therefore the interview was a bit tricky.
One part of the interview related to estimating market size. They asked me to estimate the number of Piano Tuning companies which are currently active in Tokyo, Paris and New Zealand. For the young readers, these are usually one-person company that tunes clients’ piano at their homes. Tuning is not required very often, maybe only every 1-2 years.
Related Blogs
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- ARM vs RISC-V: Beginning of a new era
- Why, How and What of Custom SoCs
- The design of the NoC is key to the success of large, high-performance compute SoCs