English
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Industry Expert Blogs
|
TSMC on Collaboration: JIT Ecosystem DevelopmentSemiWiki - Paul McLellanMar. 27, 2013 |
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry's Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.
This doesn't work any more. Since then each process generation has a major discontinuity:
- 45nm: power must be addressed
- 28nm: high-K metal gate
- 20nm: double patterning
- 16nm: FinFET
- 10nm: multiple patterning and spacer
Related Blogs
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Re-defining Collaboration
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Let's Talk PVT Monitoring: Understanding Your Chip's Age
- Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing