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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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FD-SOI Can Deliver Leading-Edge European IC Process TechnologyMannerisms - David MannersMay. 22, 2013 |
Next month customers can start prototyping on STMicroelectronics’ 28nm FD-SOI process which delivers 30% better performance than 28nm bulk CMOS, according to ST’s CTO and CMO Jean-Marc Chery.
From there the planned progress down the micron trail to 14nm is dramatic: another 30% improvement at the same operating voltage at 14nm; a 50% reduction in power at the same speed at 14nm; and a 40% reduction in die area at 14nm.
The figures can be further improved by biassing. Forward body bias on 14nm FD-SOI gives another 15% performance at the same operating voltage; reverse body bias reduces power by another 10% while maintaining the same speed.
