Industry Expert Blogs

Something that happened a while ago to ASICs has now hit FPGAs. What is it? It’s the dominance of routing delay in determining design performance. Over the years, Dennard scaling increased transistor speed while Moore’s-Law scaling increased transistor density per square mm. Unfortunately, it works the other way for interconnect. As wires become thinner and flatter with Moore’s-Law scaling, they get slower. Eventually, transistor delay shrinks to insignificance and routing delay dominates. With the increasing density of FPGAs and with the entry of Xilinx UltraScale All Programmable devices into the realm of ASIC-class design, the same problem has appeared. UltraScale devices have been re-engineered to overcome this problem but the solution wasn’t easy and it wasn’t simple. Here’s what it took.

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