MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
Complete IP port-folio built in less than two years!SemiWiki - Eric EsteveDec. 19, 2013 |
We have posted several blogs related to Cadence IP strategy, or I should say new strategy. Each of these blogs was dealing with a particular product, like PCI Express gen-3 Controller IP, latest DDR4 Memory Controller or Wide I/O. This approach was equivalent to describe trees, one after one, and finally ignoring the forest! It’s possible to define a date, the T0 when Cadence has decided to consider implementing this new strategy to develop IP business: at the end of Q1 2012, when martin Lund came on board as Senior VP, IP Group. Since then, in about 20 months, Cadence has made numerous acquisitions: Cosmic Circuits, Evatronix, the SerDes Design Team of PMC Sierra and Tensilica, the latest being the most expansive and also the most ambitious. Engaging in the DSP/CPU IP core business is certainly a strong signal to the market that Cadence takes IP seriously! As far as I am concerned, I think that Cadence positioning in the Interface IP market is also a strong signal, and could be even more rewarding in term of volume of business on the mid-term, or within three to five years.
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