Aeonic Generate Digital PLL for multi-instance, core logic clocking
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SoC Integration MistakesSemiconductor Engineering - Ed SperlingFeb. 27, 2014 |
Experts at the Table, Part 2: Why making assumptions about use cases and thinking outside the box can create disasters—and where the pain really hits.
Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion.
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