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Why 450mm Will Be Pushed-Back Even FurtherEETimes Blog - Zvi Or-Bach, MonolithIC 3D, & Ben Louie, Zeno SemiconductorsMar. 03, 2014 |
A Must-See Chart From ISSCC2014
The chart shown below was presented at ISSCC 2014 by Dinesh Maheshwari, CTO of the Memory Products Division at Cypress Semiconductors. The slide clearly illustrates that embedded SRAM ("eSRAM") scaling is broken.
Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let's discuss this further…
