400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Industry Expert Blogs
Interested in Accelerating Your Next SoC Design?Express Yourself - Scott KnowltonJun. 05, 2014 |
As I put the final touches on preparations for the PCI-SIG Developer’s Conference and getting ready to show you multiple demos for our recently announced support for PCI Express 4.0 there are exciting developments happening from Synopsys that will make your next SoC design easier. Let’s face it. Your goal is to build a product and there are multiple steps that have to be completed before the product is done while doing this under increasingly shorter time to market goals. This means that we are trying to do as many tasks as possible in parallel and they need to stay coordinated. Today, Synopsys announced our new IP Accelerated Initiative that focuses on enabling designers to incorporate IP into your SoC design flow at multiple levels of the design process by using a coordinated solution between IP prototyping kits, software development kits and customized IP subsystems.
The new DesignWare IP Development Kits provide a proven reference design for the IP preloaded onto a HAPS-DX prototyping system and a software development platform running Linux OS with reference drivers.
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