Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
D-PHY, M-PHY & C-PHY? First Look at Testing MIPI's Latest PHYEETimes Blog - Chris Loberg, Senior Technical Marketing Manager, TektronixSep. 02, 2014 |
One of the significant advantages of MIPI Alliance standards is the separation of the physical or PHY layer from the protocol layer. This approach contrasts with USB, PCI Express, or SATA, where these layers are specific to a particular protocol, and provides much needed-flexibility to deal with the many sensors and peripheral devices found in a typical mobile device while preserving the core PHY objectives of power conservation with headroom for higher data throughput.
To date, MIPI has published 30 different specifications but it only has two PHY specifications: D-PHY and M-PHY. All the display, camera, RF, storage interfaces, etc. layer on top of just these two PHYs. MIPI sees M-PHY as the high-performance PHY with speeds up to 5.8 Gbps while D-PHY is more for cameras and displays and lower-speed applications.
With low-power operation, high-performance, and flexible protocol support, it would appear that the MIPI canvas is a done deal. But, as with all things in technology, especially mobile technology, it's never that simple. Now MIPI is in the process of releasing a third PHY standard called C-PHY.
Does the world need another MIPI PHY?
Related Blogs
- Empowering AI-Enabled Systems with MIPI C/D-PHY Combo IP: The Complete Audio-Visual Subsystem and AI
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- Digitizing Data Using Optical Character Recognition (OCR)
- Let's Talk PVT Monitoring: Thermal Issues Associated with Modern SoCs - How Hot is Hot?